1. Field of the Invention
This invention relates to a semiconductor device and a fabricating method for the same.
2. Description of the Related Art
When a CMOS (Complementary Metal-Oxide-Semiconductor) device with a gate length of sub-micron (0.1 micrometer) generation is fabricated, there is a high possibility that silicon used for a generation before the above cannot be utilized for a gate electrode as it is.
The first reason thereof is that because silicon has a relatively high specific resistance of several tens Ω/□, RC delay cannot be disregarded in device operation if it is used as a gate electrode. For a device whose gate length is in the sub-micron generation, it is thought that the RC delay cannot be negligible unless the specific resistance of the gate electrode is 2 Ω/□ or less.
Furthermore, as the second reason of the above, there is a problem that the silicon gate electrode gets depleted. This is the phenomenon that solubility of the dopant impurity added in the silicon is limited to the extent of 1×1020 per cubic centimeter at most and a depletion layer of a finite length comes to expand in the silicon gate side at the interface between the silicon gate electrode and a gate insulating film.
Because this depletion layer becomes practically a capacitance connected in series to the gate insulating film, the capacitance results in being accumulated to the gate insulating film. The accumulated capacitance is to be 0.3 nm (nanometer) in thickness calculated in terms of a silicon oxide film. The gate insulating film for a future device ought to be 1.5 nm in thickness calculated in terms of a silicon oxide film, so that the thickness of 0.3 nm of the accumulated capacitance calculated in terms of a silicon oxide film cannot be ignored.
On the other hand, decreasing the resistance of the silicon gate electrode is being tried by means of adding an impurity (such as phosphorus or boron) in high density thereto. However the thickness of the gate insulating film is required to be not greater than 1.5 nm calculated in terms of a silicon oxide film, so that a problem that the impurity of high density passes through the thin-filmed gate insulating film and reaches the silicon substrate becomes obvious. Therefore, a problem arises that the density of the impurity deviate from the designed value and then the threshold voltage gets varied.
In view of the above, it has been thought that a metal with a high melting point such as molybdenum, tungsten, tantalum or their nitrides is utilized for the gate electrode. This is so-called metal gate technology.
The metal gate has a low specific resistance compared to silicon in principle, so that the RC delay can be taken no account. In addition, because no depletion layer generates theoretically in the metal gate, any capacitance accumulated thereto does not take place. Furthermore, the metal gate is expected to be able to solve some problems concerning the silicon gate. For example, the problem that impurity penetrates to the gate insulating film never occurs, because the metal gate does not require addition of any impurities to decrease the resistance thereof.
However, the metal gate has some particular problems described below when the CMOS devices are prepared.
When the CMOS devices are formed, so-called dual φ (phi) metal gate technology, in which a metallic material having a work function of p+ silicon and a metallic material having a work function of n+ silicon are employed as a gate electrode of a p channel MOS transistor and a gate electrode of an n channel MOS transistor respectively, has been proposed.
The method mentioned above can be expected to control effectively the threshold voltage of the p channel MOS transistor and that of the n channel MOS transistor. However the dual φ metal gate is restricted by some conditions where a metallic material having a work function of p+ silicon and a metallic material having a work function of n+ silicon must be found and moreover those materials must be heat resistant, so that it will be quite difficult to find combination of the appropriate materials.
Moreover, even if two kinds of metallic materials having heat resistance and an appropriate work function can be found, there is a disadvantage that complicates fabricating process of LSI because the gate electrode of the p channel MOS transistor and that of the n channel MOS transistor need to be formed by separate steps from each other for the fabricating process.
As mentioned above, the RC delay cannot be disregarded because a conventional silicon gate electrode has a high specific resistance, and consequently results in a decrease of capacitance thereof caused by depletion of the silicon gate electrode. Besides, there are more problems that if an impurity is doped to lower the resistance, the impurity penetrates the gate insulating film out of the silicon gate electrode, so that the threshold voltage thereof gets fluctuated.
Furthermore, in a method where the n channel MOS and the p channel MOS employ two kinds of metallic gates (dual φ metal gate technology) as the gate electrodes, not only it is predicted that discovering combination of metallic materials used for the gate electrodes of the p channel MOS transistor and the n channel MOS transistor is difficult, but also there is a problem that the fabricating process thereof gets complicated.